Memory cells of a dynamic random access memory (DRAM) include a storage capacitor for storing an electrical charge which represents an information to be stored, and an access transistor for addressing the storage capacitor. The access transistor includes a first and a second source/drain regions, a conductive channel adjacent to the first and second source/drain regions as well as a gate electrode controlling an electrical current flowing between the first and second source/drain regions. The transistor usually is formed in a semiconductor substrate. The information stored in the storage capacitor is read out by addressing the access transistor. There is a lower boundary of a channel length of the access transistor, below which the insulation properties of the access transistor in an non-addressed state are non-sufficient. The lower boundary of the effective channel length Leff limits the scalability of planar transistor cells having an access transistor which is horizontally formed with respect to the substrate surface of the semiconductor substrate.
A specific transistor concept refers to a FinFET. The active area of a FinFET usually has the shape of a fin or a ridge which is formed in the semiconductor substrate between the first and second source/drain regions. A gate electrode encloses the fin at two or three sides thereof. In particular, in a double-gate FinFET, two gate electrodes are disposed at the two lateral sides of the active area. In addition, a top gate can be provided, which is formed on the top side of the active area. The portions of the gate electrode which portions laterally extend along the active area can extend to a predetermined depth. In particular, the lateral portions of the gate electrode can be provided so as to extend to a depth which is above half of the depth of the isolation trench which is disposed adjacent to the active area.
In currently-used DRAM memory cells, the storage capacitor can be implemented as a trench capacitor. In such a trench capacitor the two capacitor electrodes are formed in a trench which extends into the substrate in a direction perpendicular to the substrate surface. According to another implementation of a DRAM memory cell, the electrical charge is stored in a stacked capacitor, which is formed above the surface of the substrate.
“Novel Body Tied FinFET Cell Array Transistor DRAM with Negative Word Line Operation for sub 60 nm Technology and beyond”, by C. H. Lee at al., 2004 Symposium on VLSI technology, Digest of Technical Papers, pp. 130 discloses a method of forming a memory cell array in which each memory cell comprises a storage capacitor which is implemented as a stacked capacitor. For forming the transistor array, first, segmented active areas are formed by known methods. Thereafter, the whole transistor array is covered by an insulating layer. For removing the insulating layer from the lateral sides of the active areas, an etching step is performed in which the peripheral portion of the memory device is masked by a block mask. In a later step, a hard mask material is deposited and patterned, thereby forming stripes which extend perpendicular to the active areas. Thereafter, the active areas are locally thinned taking the patterned hard mask layer as an etching mask. The patterned hard mask layer is as well taken as a mask for a subsequent implantation step. In a later step, stacked capacitors are formed by usual methods.
For forming a memory cell array comprising trench capacitors, the problem arises, that, when globally removing the insulating layer from the array portion of the memory cell array, also a trench top oxide which fills the upper portion of the capacitor trenches is removed.
In addition, problems with the buried strap, the connection between the trench capacitor and the array device, can arise. To be more specific, by removing the oxide on top of the buried strap, problems with the gate conductor formation can be caused. In particular, if a 8 F2 checkerboard array is implemented, the passing word line is running over the deep trenches. If no trench top oxide is left on the trenches, only the gate oxide insulates the passing word line from the deep trench fill which is not sufficient.